1. Field of the Invention
The present invention relates generally to memory cell structures formed within microelectronic fabrications. More particularly, the present invention relates to enhanced performance memory cell structures formed within semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
Common in the art of microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, is the use and the fabrication of memory cell structures, and in particular dynamic random access memory (DRAM) cell structures. Dynamic random access memory (DRAM) cell structures typically comprise a field effect transistor (FET) device formed within and upon a semiconductor substrate, where one of a pair of source/drain regions within the field effect transistor (FET) device has formed thereover and electrically connected therewith a storage capacitor. Within a dynamic random access memory (DRAM) cell structure, a gate electrode within the field effect transistor (FET) device serves as a wordline which provides a switching function for charge introduction into and retrieval from the storage capacitor, while the other of the pair of source/drain regions within the field effect transistor (FET) device serves as a contact for a bitline conductor layer which introduces or retrieves charge with respect to the storage capacitor.
While the dynamic random access memory (DRAM) cell structure has clearly become ubiquitous in the art of semiconductor integrated circuit microelectronic fabrication, and is thus essential in the art of semiconductor integrated circuit microelectronic fabrication, the dynamic random access memory (DRAM) cell structure is nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication.
In that regard, as semiconductor integrated circuit microelectronic fabrication integration levels have increased and semiconductor device and patterned conductor layer dimensions have decreased, it has become increasingly difficult in the art of semiconductor integrated circuit microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, to fabricate dynamic random access memory (DRAM) cell structures with decreased dimension and enhanced performance.
It is thus desirable in the art of microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, to provide methods and materials through which there may be fabricated memory cell structures with decreased dimensions and enhanced performance.
It is towards the foregoing object that the present invention is directed.
Various memory cell structures having desirable properties, and methods for fabrication thereof, have been disclosed in the art of semiconductor integrated circuit microelectronic fabrication.
Included among the memory cell structures, but not limited among the memory cell structures, is the memory cell structure disclosed within Huang, in U.S. Pat. No. 6,096,595 (a memory cell structure having formed therein a self aligned conductor contact structure interposed between a pair of polycide gate structures, where the memory cell structure is further integrated and embedded with respect to a metal oxide semiconductor (MOS) logic device structure having formed therein a salicide gate structure).
Desirable in the art of microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, are additional methods and materials which may be employed for fabricating memory cell structures of decreased dimensions and enhanced performance.
It is towards the foregoing object that the present invention is directed.
A first object of the invention is to provide a memory cell structure for use within a microelectronic fabrication.
A second object of the present invention is to provide a memory cell structure in accord with the first object of the present invention, wherein the memory cell structure may be fabricated with decreased dimensions and enhanced performance.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a memory cell structure. To practice the method of the present invention, there is first provided a semiconductor substrate. There is then formed within and upon the semiconductor substrate a field effect transistor (FET) device comprising a gate dielectric layer formed upon the semiconductor substrate, a polysilicon gate electrode formed upon the gate dielectric layer, a sacrificial capping layer formed upon the polysilicon gate electrode, a pair of source/drain regions formed within the semiconductor substrate and separated by the gate electrode and a pair of spacer layers adjoining a pair of opposite edges of the gate electrode. There is then formed over the semiconductor substrate and passivating the field effect transistor (FET) device a passivating layer. There is then formed through the passivating layer, while employing the pair of spacer layers and the sacrificial capping layer as a mask, at least one self aligned contact via accessing at least one of the source/drain regions. There is then forming into the self aligned contact via a conductor stud layer. There is then stripped from over the substrate the passivating layer and the sacrificial capping layer to leave exposed a top surface of the polysilicon gate electrode separated from the conductor stud layer by one of the pair of spacer layers. Finally, there is then formed upon the exposed top surface of the gate electrode a silicide layer while employing a salicide method.
The present invention provides a memory cell structure for use within a microelectronic fabrication, wherein the memory cell structure may be fabricated with decreased dimensions and enhanced performance.
The present invention realizes the decreased dimensions of the memory cell structure by fabricating the memory cell structure with a self aligned conductor stud layer formed within a self aligned contact via. The present invention realizes the enhanced performance of the memory cell structure by forming upon a polysilicon gate electrode within the memory cell structure a silicide layer while employing a salicide method which provides the silicide layer with an decreased contact resistance in comparison with silicide layers formed other than by employing salicide methods.